The invention relates to a D-type flip-flop and to a D-type flip-flop with an activation input.
In integrated circuits having a large number of flip-flop circuits, the required chip area is determined to a significant extent by the area of the flip-flops. In the circuit to be integrated, a large number of required flip-flops lead to a very large chip area or have the effect that it is not possible for the entire circuit to be integrated in a chip.
The flip-flop circuits are, usually, constructed from a master latch and a slave latch, the master latch accepting a data signal present at the data input with a first edge and the slave latch accepting the data signal with a second edge, from where it can, then, be tapped off at a non-inverting and an inverting output. For such a purpose, in each D-type flip-flop, an inverted clock signal can be formed from the clock signal present by an inverter circuit and a non-inverted clock signal can be formed from the inverted clock signal by a further inverter circuit so that the non-inverted clock signal and the inverted clock signal can be made available to the master latch and to the slave latch.
Usually, both master latch and the slave latch comprise a clock-level-controlled holding element into which data are accepted with the aid of the first and the second clock edge, respectively, and are stored permanently, i.e., statically, therein depending on the clock level. Making the non-inverted clock signal and the inverted clock signal available for the master latch and the slave latch means that at least two or four transistors are required, which increase the area required in the integrated circuit.